1. Field of the Invention
The invention relates to the field of dynamic MOS RAMS.
2. Prior Art
Metal-oxide-semiconductor (MOS), integrated circuit memories including random-access memories (RAMS) are known in the art. These memories are fabricated utilizing known MOS technology with the entire memory fabricated on a single silicon substrate. Such memories are typically either static or dynamic. The static RAMS generally employ bistable circiuts, such as flip-flops for memory cells. Such circuits require a number of devices, for example, several field-effect transistors, for each cell. The dynamic RAMS often employ memory cells which rely upon capacitive storage. These memories require periodic refreshing since the capacitive storage is transient. To obtain a higher density RAM the presently disclosed RAM, in addition to some prior art RAMS, utilizes memory cells having a single active device for each cell. This device is generally a field-effect transistor which is used to gate or select a capacitive storage means. For an example of a prior art use of single active device memory cells, see U.S. Pat. No. 3,533,089.
One method of producing more economical memories is to increase density such that for a given area of substrate more storage is provided. However, as the device density increases, power consumption per bit of storage becomes more critical and moreover, for single active device cells, noise becomes more of a problem.
In some dynamic MOS RAMS which employ a single active device for each memory cell, a single input/output bus is employed. This bus is coupled to all the bit-sense lines in the array through the row decoders. The use of a single input/output bus while simplifying the chip architecture, provides inherent noise rejection problems. An example of one such memory employing a single input/output bus is disclosed in co-pending application Ser. No. 520,797 filed Nov. 4, 1974 now U.S. Pat. No. 3,959,781. and assigned to the assignee of this application. In the presently disclosed memory a pair of input/output lines are employed which are coupled to alternate pairs of the bit-sense lines. This provides additional advantage through the use of a bistable input/output latch with a differential amplifier and push-pull buffer to provide better noise rejection.
In MOS RAMS employing single active device memory cells, the bit-sense lines of the array are often bisected with bistable sense amplifiers. It is known in the prior art that the effectiveness of these amplifiers may be increased by delaying conduction through the amplifier loads after the amplifier has been activated. In this manner the loads present very high impedance, thus providing higher gain. A MOS RAM employing such a technique is disclosed in co-pending application Ser. No. 569,927 filed Apr. 21, 1975, now U.S. Pat. No. 3,978,459 assigned to the assignee of this application. In the presently disclosed MOS RAM the sense amplifiers are activated with a signal having a dual slope to provide improved noise rejection and gain. This is accomplished by activating the pull-down devices of the sense amplifier to a lesser extent during the first slope while the pull-up devices are in the high impedance mode, thus facilitating high gain, lower power operation of the sense amplifier. During the second slope the pull-down devices on the sense amplifier conduct more heavily, at the same time the pull-up devices are driven into a higher conduction range. This changes the sense amplifier mode to lower gain, high power operation. Hence, the same devices provide the high gain requirement during the initial stage of the operation, and high drive capability after the basic signal has been sensed.
The MOS RAM of the present invention employs several other novel circuits and techniques to provide a higher speed MOS RAM which consumes less power and which has improved noise and pattern sensitivity characteristics.